1. Field of the Invention
The present invention relates to an arrangement for converting a binary input signal into corresponding inphase and quadrature phase signals, and more specifically to an arrangement suitable for use in GMSK (Gaussian minimum shift keying) modulation.
2. Description of the Related Art
It is known in the art to use an arrangement as shown in FIG. 1 to convert a binary input signal into inphase and quadrature baseband signals for GMSK quadrature modulation.
Before discussing the arrangement illustrated in FIG. 1 detail it is deemed advantageous to briefly discuss the principle underlying the same.
It is known that a phase .phi.(t) of a GMSK modulating signal is represented by equation (1). ##EQU1## wherein T: bit period;
d.sub.i : i-th incoming data [0, 1]; PA0 a.sub.i : i-th symbol [+1, -1](=1 -2d.sub.i); ##EQU2## B: 3 dB cut-off frequency of GMSK baseband filter; and ##EQU3## Equation (1) can be approximated as equation (2). ##EQU4## wherein M is an appropriate natural number. PA0 (a) d.sub.k ; PA0 (b) M bits which precede d.sub.k ; PA0 (c) M bits which follow d.sub.k ; and PA0 (d) P.sub.k and q.sub.k defined by equation (7).
If M.gtoreq.2, a phase error using the approximation equation (2) is very small (viz., within .+-.0.2.degree.). Equation (2) can be rewritten using a given positive integer k indicating the number of data as follows. ##EQU5## where T(k-1/2)&lt;t&lt;T(k+1/2).
.phi..sub.k (t) represents a phase of a symbol a.sub.k, viz., the phase during a time duration defined between T(k-1/2) and T(k+1/2).
Designating the first and second terms of equation (3) by X.sub.k (t) and Y.sub.k respectively, the following equation is given EQU .phi..sub.k (t)=X.sub.k (t)+Y.sub.k ( 4)
It is understood from equation (3) that X.sub.k (t) is determined by a.sub.k and N symbols preceding and following a.sub.k (viz., (N+1) symbols in total). That is to say, X.sub.k (t) is determined by d.sub.k and the M-bit preceding and following d.sub.k (Viz., (M+1)-bit in total). On the other hand, Y.sub.k can be represented by EQU Y.sub.k =Y.sub.k-1 +(.pi./2)a.sub.k-M-1 ( 5)
Accordingly, Y.sub.k is defined by the past status of a symbol and hence becomes uncertain depending on initial conditions. However, the GMSK modulation is in fact implemented by a phase difference between adjacent symbols and therefore, there is no need for considering the absolute value of each phase. This means that if Y.sub.k satisfies the difference equation (5), the initial value thereof can be set to an arbitrary one. Since a.sub.i takes an either value of +1 or -1, if the initial value is assumed 0, Y.sub.k assumes one of the four values as shown in the following. EQU Y.sub.k =0, .+-..pi./2, .pi.(radian) (6)
Let us introduce two 2-bit variables of state P.sub.k, q.sub.k and have Y.sub.k correspond to them as follows. ##EQU6## FIG. 2 is a sketch showing the transitions of the state of Y.sub.k which can be obtained from equations (5) and (7). In FIG. 2, the values of Y.sub.k (0, +.pi./2, .pi. and -.pi./2) are respectively indicated within circles. It is understood, from equations (3), (4) and FIG. 2, that .phi..sub.k (t) is determined by the following:
On the other hand, the in-phase signal (I.sub.k (t)) and the quadrature signal (Q.sub.k (t)) are given by ##EQU7## By defining discrete values of time as shown in equation (9), EQU t.sub.L =T(k-1/2)+(T/N)L+T/2N (9)
wherein L is a discrete variable (L=0, 1, . . . , (N-1)), and N is a positive integer.
Thus, we obtain ##EQU8## X.sub.k (t.sub.L) is determined by a.sub.k-M, a.sub.k-M+1, . . . , a.sub.k, . . . , a.sub.k+M-1, a.sub.k+M, and L. Accordingly, each of .phi..sub.k (t.sub.L), I.sub.k (t.sub.L) and Q.sub.k (t.sub.L) is determined by d.sub.k-M, d.sub.k-M+1, . . . , d.sub.k, . . . , d.sub.k+M-1, d.sub.k+M, P.sub.k, q.sub.k and L.
It follows that the in-phase and quadrature signals (I.sub.k (t.sub.L), Q.sub.k (t.sub.L)) can be obtained by a binary input data d.sub.i using two ROMs which respectively store EQU I.sub.k (t.sub.L)=cos .phi..sub.k (t.sub.L) EQU Q.sub.k (t.sub.L)=sin .phi..sub.k (t.sub.L).
In this case, the data within the ROMs are derived using an address determined by d.sub.k-M, d.sub.k-M+1, . . . , d.sub.k, . . . , d.sub.k+M-1, d.sub.k+M, P.sub.k q.sub.k and L.
The above-mentioned principle is utilized in configuring the known arrangement shown in FIG. 1 wherein it is assumed that M=2 and N=8.
FIG. 1 will be discussed with reference to FIG. 3. A shift register 20 receives the binary input data d.sub.i via an input terminal 22 in synchronism with a clock signal /A2 and shifts the data d.sub.i according to the clock signal /A2. Throughout the instant specification and claims, the symbol "/" preceding "A2" (for example) denotes an inverted "A2" and corresponds to a bar over "A2" in the drawing. The clock signal /A2 is derived from an output terminal Q2 of an octal counter 24 via an inverter 26.
The shift register 20 outputs d.sub.k-2, d.sub.k-1, d.sub.k, d.sub.k+1 and d.sub.k+2 in this particular case (viz., M=2) from five shift stages, which are inputted to each of two ROMs 28 and 30 as the upper 5 bits (viz., A5, A6, A7, A8 and A9) of a 10-bit address signal (denoted by ADD-28, ADD-30). The ROM 28 pre-stores the data of cos .phi..sub.k (t.sub.L) while the ROM 30 pre-stores the data of sin .phi..sub.k (t.sub.L).
The variables of state P.sub.k and q.sub.k are obtained by ##EQU9## wherein d.sub.k-M-1 equals d.sub.k-3 (M=2) and .sym.represents a logical operation of exclusive-OR.
A sequential logic 32 is an arrangement for implementing the logical operations given by equation (11) and which includes two exclusive-OR gates 34, 36 and two D-type flip-flops 38, 40. The sequential logic 32 is supplied with d.sub.k-2 and the timing clock /A2 and outputs the state variables p.sub.k and q.sub.k both of which are applied to the ROMs 28, 30 as address bits A3, A4. The operation of the sequential logic 32 will readily be understood and hence further description thereof will be omitted for brevity.
The octal counter 24 receives, via an input terminal 28, a clock signal CLK whose timing chart is shown in a row labelled CLK in FIG. 3. The counter 24 produces three address bits A0, A1 and A2 at the output terminals Q0, Q1 and Q2, which correspond to the discrete-time variable L and which are applied to the ROMs 28 and 30 as lower 3-bit of the addresses (viz., ADD-28, ADD-30).
FIG. 3 shows a timing chart of each of the above-mentioned signals. For the convenience of a better understanding, a logical equation p.sub.k =p.sub.k-1 .sym.q.sub.k-1 .sym.d.sub.k-3 is inserted in the drawing.
Each of the ROMs 28, 30 output respectively the data according to the addresses ADD-28, ADD-30 applied thereto. Two digital-to-analog converters (DACs) 42, 44 are provided for converting the digital outputs of the ROMs 28, 30 into corresponding analog signals, respectively. The analog signals thus obtained are derived via output terminals 46, 48 to an external circuit (not shown), and are used to modulate a carrier signal as is well known in the art.
However, the aforesaid known technique has encountered the problem in that each of the ROMs 28, 30 must have an undesirably large storage capacity. More specifically, the number of address bits for each of the ROMs 28, 30 is ten (10) in the FIG. 2 arrangement, and hence the number of words required for each of the ROMs 28, 30 reaches 1024-word. In the case where the word length of each of the ROMs 28, 30 is 8-bit, the total number of bits required for the ROMs 28, 30 amounts to 16k-bit. Viz.,: EQU (1024-word).times.(8-bit/word).times.2=16k-bit
Accordingly, requiring such a large memory leads to undesirably large memory chip sizes. It is therefore highly desirable to decrease the memory size of each of the ROMs 28, 30 for effectively reducing memory manufacturing costs, etc.